A Local Area Network, or (LAN), is a communications systems that provides a connection among a number of independent computing stations within a small area, such as a single building or group of adjacent buildings. One type of network structure uses one or more repeaters in a star topology, with each repeater having several ports. A data packet received at one port is retransmitted to all other ports of the repeater. Each repeater in turn restores timing and amplitude degradation of data packets received at one port and retransmits the packets to all other ports.
Traditional Ethernet networks (10 BASE-T) operate at 10 Mb/s Ethernet protocol, as described by IEEE Standard 802.3; the majority of Ethernet interfaces currently operate at this data rate. However, a newer Ethernet standard, under IEEE standard 802.3 u, accomplishes the faster operation of 100 BASE-T systems, at a 100 Mb/s data rate (i.e., a 125 Mb/s encoded bit rate) using unshielded twisted pair (UTP) physical media. The 100 BASE-T standard defines operation over two pairs of category 5 UTP (100 BASE-TX) and over four pairs of category 3 UTP. The 100 BASE-FX network medium, covered by the 100 BASE-T standard, allows operation over dual fiber optic cabling.
Ethernet protocol provides for a Media Access Control (MAC), enabling network interface devices at each network node to share accesses to the network medium. One type of connection, termed a Media Independent Interface, or MII, connects the MAC to a physical layer (PHY) transceiver configured for a particular network medium, e.g., 10 BASE-T, 100 BASE-FX, or 100 BASE-TX. The physical layer transceiver is configured for converting the MII protocol signals output by the MAC into analog network signals, such as Multiple Layer Transition-3 (MLT-3) signals for 100 Mb/s Ethernet networks, or Manchester-encoded signals for 10 Mb/s Ethernet networks. (Networks often use several PHY devices operating over different media types.) Included in such transceiver is an autonegotiation unit that determines the speed of operation of the link partner on the network medium using well-known auto-negotiation techniques. Additional details regarding autonegotiation are disclosed in Breyer et al., "Switched and Fast Ethernet: How It Works and How to Use It", Ziff-Davis Press, Emeryville, Calif. (1995), pp. 60-70, and Johnson, "Fast Ethernet: Dawn of a New Network", Prentice-Hall, Inc. (1996), pp. 158-175.
FIG. 1 is a block diagram of an exemplary LAN architecture which can transport network data at different data rates. As shown in FIG. 1, the network 5 includes a network switch 10, a repeater 12 operating at a first data rate such as 10 Mb/s, a second repeater 14 operating at a second data rate such as 100 Mb/s, and a multiple port physical layer transceiver 16. The switch 10 and the repeater 12 transfer network data via a data link 18 operating at the first data rate of 10 Mb/s. The switch 10 and the repeater 14 transfer data via a different data link 20 operating at the second data rate of 100 Mb/s. The repeaters 12 and 14 transfer data to and from the network transceiver 16 via repeater interfaces 22 and 24 operating at 10 Mb/s and 100 Mb/s, respectively. As recognized in the art, the repeater 12 may also transfer network data to individual network workstations 26 operating at 10 Mb/s via a shared medium 28, and the repeater 14 may transfer data to network workstations 30 operating at 100 Mb/s via a network medium 32. Transceiver 16 is a multiple port physical layer transceiver which enables multiple workstations 26', 30' having different data rates of 10 Mb/s and 100 Mb/s, respectively, to be connected to a single PHY unit for communication with the repeater interfaces 22 and 24.
The transceiver 16 includes a driver stage which imparts an analog waveform onto a network medium, right before a magnetic transformer. The driver stage of the transceiver 16 receives an output of a digital to analog converter (DAC) serving as a current source, and amplifies the current like a class AB type amplifier; i.e. push-pull type of circuit. Since the driver stage must drive both the 10 BASE-T and 100 BASE-TX standard, the same impedance will be driven with the same termination whether in 10 BASE-T or 100 BASE-TX mode.
For the 10 BASE-T mode, approximately 2.5 volts (actually 1.8 volts) has to be driven and the maximum frequency of the waveform is 10 MHz. The waveform is composed mostly of sine waves; i.e., it has a very smooth sinusoidal type output. A 10 BASE-T waveform is shown in FIG. 2, and can drive a series of nodes. This waveform includes 10 MHz and 5 MHz pules characterized by Manchester data and needs to be generally smooth. The waveform varies between 5 MHz and 10 MHz impulses because the digital aspect of a Manchester waveform is that there is a coding such that there is always a transition (e.g., zero crossing) in the middle. A rising transition is characterized as a "1", and a falling transition is characterized as a "0". When a series of "1s" are transmitted in a row, there will be a 10 MHz waveform 10 as shown at points A, B and C of FIG. 2. However, as a transition to a "0" occurs at point D, the waveform between points C and D will continue as a 5 MHz waveform 12. If the end transition at point E is a "1", the waveform will remain a 5 MHz pulse so it starts to resemble a 5 MHz pulse rather than a 10 MHz pulse, but the waveform is a combination of "1s" and "0s". If all "0s" or all "1s" are transmitted, 10 MHz pulses are obtained. If a combination of "1 0 1 0" is transmitted, the waveform will appear as 5 MHz pulses.
An objective in transmitting Manchester data is not to convert the pulses into complex digital waveforms having very sharp edges. Consequently, there will be a function to smooth and precondition the waveform to compensate for line characteristics of filtering high frequency components more than low frequency components, i.e., de-emphasize the low frequency components which is the 5 MHz waveform. Thus, the signal of FIG. 2 needs to be contoured relative to the line of the transmission medium to that of signal 14 of FIG. 3. In addition, the Manchester output needs to be filtered so that each step in the waveform 14 is a 5 nanosecond (ns) step. Thus, there is a digitizing resolution of sampling at 5 ns resulting in 20 samples per 100 ns period of the 10 MHz waveform 10.
In the 100 BASE-TX mode, about 1 volt has to be driven as compared to about 2.5 volts for the 10 BASE-T mode, and an MLT-3 waveform is used. A MLT-3 (100 MHz) is shown in FIG. 4 and is basically a three-level waveform (digital waveform) converted from Non-Return to Zero Interface (NRZI) data. The waveform has certain rise time and fall time constraints depending whether the signal is transitioning from a "0" to a "1", or a "1" to a "0", and the level of the signal. When a signal is converted from NRZI to MTL-3, every time there is a "1" in NRZI, the MLT-3 signal makes a transition. If there is a "0", then there is no transition. The data in 100 BASE-TX mode is basically 125 MHz serial data which corresponds to 8 ns. Thus, the MLT-3 waveform has a transmit sampling point every 8 ns. Each sampling point is capable of generating a transition going from "0" to "1", or "1" to "0". Therefore, each time there is a transition in FIG. 3, there is a sampling.
Since the data in 100 BASE-TX mode is basically 125 MHz serial data, a driver in the driver stage has to be able to transition from "0" to "1" with a rise time between 3 to 5 ns. Consequently, there is a fairly abrupt change in the edge rate between 3-5 ns. With MLT-3 voltages, the edge rates and transitions are much faster that what is needed in the 10 BASE-T mode. The faster the edge rates are in the 10 BASE-T mode, the more discontinuity there is since, when the edge rate exceeds a certain value, there are excess harmonics (ringing) at the upper frequency range.
Thus, in the 100 BASE-TX mode with MLT-3, a driver in the driver stage needs to have a fast response as compared to the 10 BASE-T mode with Manchester data where the driver stage needs to have a slower response to avoid harmonics. In addition, in the 10 BASE-T mode, a driver of the driver stage needs more gain (capable of driving a larger amount of voltage) than in the 100 BASE-TX mode. Thus, in the 10 BASE-T mode, important factors for a driver of the driver stage are a high gain and a slow response, whereas in the 100 BASE-TX mode, important factors for a driver of the driver stage are low gain, but a fast response. Consequently, the important factors for transmitting data in 10 BASE-T mode and 100 BASE-TX mode are opposite each other.
A conventional driver is shown in FIG. 5A(1) and comprises current mirror 30 formed of MOS devices. Current mirror 30 is a moving current mirror which converts current to voltage and then voltage back into current. In the current mirror 30, imparting a certain voltage on the gate (G) of transistor MM1 causes certain current to flow from the source (S) to the drain (D) of transistor MM1. Since the gate (G) of transistor MM1 is tied to its drain (D) and to the gate (G) of transistor MM2, the same gate to source voltage imparted on transistor MM1 is similarly imparted on transistor MM2.
The conventional driver 30 amplifies current because of the high current drive requirements of a network driver. More specifically, there is a need to amplify a small current that is present in the driver chip (5 or 6 milliamps for the "high" analog current) to 70-80 milliamps of current on the output. In the 10 BASE-T mode, the driver current gain should be 1:16, while in 100 BASE-TX mode, the driver current gain should be 1:8, half that of the 10 BASE-T mode.
Referring to the current (I) vs. voltage (V) curve shown in FIG. 5B, both MM1 and MM2 of driver 30 need to be operating in the saturation region 22 (nonlinear region) on the curve 20 so that the drain source voltage V.sub.DS will be -V.sub.T above the gate source voltage V.sub.GS. This condition is important so that the drain voltage V.sub.D does not rise so far that it starts falling off the flat region 22. In this flat region 22 of the I-V curve, a certain amount of current is obtained when a certain amount of gate voltage is imparted. Referring back to FIG. 5A(1), the current mirror 30 operates as follows. When current (I) flows out of transistor MM1, a certain gate to source voltage is established to supply this current, i.e., the voltage will fall to a level which sustains the amount of current flowing out of the transistor. When this voltage level is reached, the gate to source voltage established for transistor MM1 will be imparted on the gate of transistor MM2. If transistors MM1 and MM2 are perfect matching transistors, the current (I) out of transistor MM2 will mirror the same amount of current out of transistor MM1.
By providing a moving current mirror formed using MOS devices, the current bearing ratio is less and therefore, response of the driver can be fast as is needed in 100 BASE-TX mode. However, as noted, above, a fast response is not needed in 10 BASE-T mode. In addition, a higher gain is necessary in 10 BASE-T mode as compared with the 100 BASE-TX mode. Thus, a driver used for the 100 BASE-TX mode would not satisfy requirements of the 10 BASE-T mode. Consequently, two separate drivers would be used for the separate modes, each designed to effect the important factors of the respective mode.
In order to simplify the circuitry and its manufacture, both drivers would use the basic design of the conventional driver 30. In order to increase the gain factor of the conventional driver 30 (as is needed in 10 BASE-T mode as compared to 100 BASE-TX mode), additional MM2 transistors can be provided in parallel. FIG. 5A(2) depicts a driver 30' with a third transistor MM3, in parallel with transistor MM2, used to double the amount of output current to satisfy the requirements of the 10 BASE-T mode. Transistors MM2 and MM3 are similar to two parallel current sources for summing node NA, and provide twice the amount of current (21). If additional mirror transistors are added, current gain would further increase. This driver configuration, however, is unsuitable for use in the 100 BASE-TX mode as it does not have a fast enough response.
Thus, two separate drivers would be provided in the driver stage, each dedicated to operate only in the respective mode. However, such arrangement increases the chip area needed for the driver stage. Consequently, there is a need to provide a single driver that can operate in both 10 BASE-T mode and 100 BASE-TX mode and effect the important factors for each mode.